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close this bookAmplifier Teaching Aid (GTZ, DED; 86 pages)
View the documentPreface
View the documentIntroduction
Open this folder and view contentsLesson 1 - Semiconductor Review
Open this folder and view contentsLesson 2 - Bipolar Transistor
Open this folder and view contentsBipolar Transistor II
View the documentFirst Evaluation
Open this folder and view contentsLesson 4 - Transistor Fundamentals
Open this folder and view contentsLesson 5 - Transistor Biasing
close this folderLesson 6 - Transistor Biasing II
close this folderLesson Plan
View the documentTransistor biasing II
View the documentVDB analysis
View the documentWorksheet No. 6
View the documentSecond Evaluation
Open this folder and view contentsLesson 7 - Small Signal Amplifier
Open this folder and view contentsLesson 8 - Small Signal Amplifier II
Open this folder and view contentsLesson 9 - Small Signal Amplifier III
Open this folder and view contentsLesson 10 - Large Signal Amplifier
View the documentThird Evaluation

VDB analysis

Design errors of 5% or less are acceptable, because of resistor tolerances.

Fig. 6-3: VDB example circuit

Find the base voltage:

Assumption: Base current is so small that it has no effect on the voltage divider.

5% error - > base current is 20 times smaller than the divider current.

VB = I * R2 = 0.82 mA * 2.2KΩ = 1.8V

VE = VB - VBE = 1.8V - 0.7V = 1.1V

VC = VCC -(RC * IC) = 10V - (3.6KΩ * 1.1 mA) = 6.04V

VCE = VC - VE = 6.04V - 1.1V = 4.94V

Checking the assumption:

5% error -->

The current gain can vary from 30 to 300.

Even under the worst case condition the calculation is within the 5% limit, hence the assumption can be done.

Summary of Process and Formulas

Divider current

Base voltage

VB = I * R2

Emitter voltage


Emitter current

Collector voltage

VC = VCC - (IC * RC)

Coll.- emitter voltage


HO: What will change if the emitter resistor increases to 2KΩ? (unchanged voltage divider)

Fig. 6-4: VDB circuit


I = 0.82 mA

VB = 1.8V

VE = 1.1V

VC = VCC - (RC * IC) = 8.02V

VCE = VC - VE = 6.92V

VDB Load-Line and Q-Point

Fig. 6-5: VDB circuit

Saturation point:

Visualize short between collector and emitter

VRC = VCC - VE = 10V - 1.1V = 8.9V

- - >

Cutoff point:

Visualize open between collector and emitter

- - > VCE (cut) = VCC - VE = 8.9V


VC = VCC - (IC * RC) = 10V - (1.1 mA * 1KΩ) = 6.04V

VCE = VC - VE = 6.04V - 1.1V = 4.94V

Now we plot these values and get the load line and the Q-point:

Fig. 6-6: Output curve with load line and Q-point

The values VCC, RC, R1, and R2 are controlling saturation current and cutoff voltage. To move the Q-point is possible by varying the emitter resistance (RC).

Get the Q-point in the Middle of the Load Line

To set the Q-point is a important preparation as you will see later on.

Effect of RE:

RE too large -- > Q-point moves into cutoff
RE too small --> Q-point moves into saturation

Q - point in the middle of the load line:

Half the value of IC (sat) and redesign RE

IC (sat) = 2.47 mA ==> 1.23 mA

Look for the nearest standard value:

===> 910 Ω

Fig. 6-7: Output curve, Q-point in the middle

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